Location: Ho Chi Minh / Ha Noi (Open to qualified candidates nationwide)
Work Mode: Remote / Hybrid options available (based on project needs)
Experience Level: Mid to Senior level
Industry: Semiconductors / VLSI
Job Summary
We are seeking a Physical Design Engineer to execute and take ownership of the RTL-to-GDSII implementation flow for advanced ASIC/SoC designs. In this role, you will handle the entire physical implementation lifecycle—from floorplanning and place-and-route (P&R) to timing closure, power integrity, and physical verification—ensuring high-quality, tape-out-ready silicon blocks.
Key Responsibilities
- Execute the complete RTL / Gate-level Netlist-to-GDSII flow for design partitions, specific blocks, or full-chip architectures.
- Take full ownership of physical design blocks, ensuring they meet strict sign-off targets and are fully prepared for tape-out.
- Manage Floorplanning and Power Planning to optimize area, performance, and routability.
- Drive Timing Closure and Static Timing Analysis (STA) to meet aggressive performance metrics.
- Implement robust Clock Tree Synthesis (CTS) and address Signal Integrity (SI) issues to eliminate cross-talk and noise.
- Achieve successful closure on Design Rule Checking (DRC) and Layout Versus Schematic (LVS).
- Run IR drop and power integrity analysis to achieve full sign-off readiness prior to tape-out.
Requirements
- Education: B.Tech / M.Tech in Electronics, Electrical, Computer Engineering, or an equivalent technical discipline.
- EDA Tool Expertise:
- Place & Route: Cadence Innovus, Synopsys IC Compiler II (ICC2), or Fusion Compiler.
Timing & Power: PrimeTime, Tempus, Voltus, or PowerReplay.
Physical Verification: Calibre, Pegasus, or IC Validator.
- Place & Route: Cadence Innovus, Synopsys IC Compiler II (ICC2), or Fusion Compiler.
- Timing & Power: PrimeTime, Tempus, Voltus, or PowerReplay.
- Physical Verification: Calibre, Pegasus, or IC Validator.
- Technical Knowledge & Flows:
- Deep understanding of RTL / Netlist-to-GDSII methodologies.
Hands-on experience with Multi-Vt / Multi-Voltage and low-power design techniques (UPF / COPF).
Familiarity with DFT-aware physical implementation.
Practical experience working on advanced nodes (28nm down to 3nm preferred).
- Deep understanding of RTL / Netlist-to-GDSII methodologies.
- Hands-on experience with Multi-Vt / Multi-Voltage and low-power design techniques (UPF / COPF).
- Familiarity with DFT-aware physical implementation.
- Practical experience working on advanced nodes (28nm down to 3nm preferred).
- Automation: Proficiency in Python, Perl, or Shell scripting for tool and flow automation.
- Soft Skills: Strong analytical capabilities, excellent debugging mindset, and effective cross-functional collaboration skills.
- Flexible Working: True hybrid or remote working arrangements tailored to project requirements, providing great autonomy.
- Financial Security: 100% full salary from your very first day of employment, a 13th-month salary, and an insurance plan calculated based entirely on your gross salary.
- Premium Healthcare: Comprehensive Medical Benefit package (Bao Viet Insurance) covering both the employee and their immediate family members.
- Generous Time Off: 18 paid leaves per year
- Global Opportunities: Work within a highly diverse, multinational network with opportunities for international travel and onsite assignments across 60 countries.
- Professional Growth: Structured internal technical and functional training programs, alongside continuous English communication development.
Client Overview
Our client is a prominent global technology corporation with a workforce of over 226,000 engineers and specialists across 60 countries. Generating over $14 billion in revenue, they deliver industry-leading engineering, digital, and AI-powered solutions to major global verticals. For semiconductor professionals, they offer a world-class VLSI environment working on cutting-edge designs, providing a collaborative ecosystem built for continuous technical growth and global exposure.
