• Location: Hanoi / Ho Chi Minh City, Vietnam
• Work Mode: Full-time (Monday – Friday) | Flexible & Fast-paced Environment
• Experience Level: 4+ - 10+ years
• Industry: Semiconductors / VLSI

Job Summary

We are seeking an experienced Design for Testability (DFT) Engineer (4+ years of experience) to lead and execute critical testability features within complex ASIC/SoC designs. In this role, you will hold technical ownership over DFT insertion and verification, while also providing mentorship to junior engineers, ensuring process compliance, and driving verification closure to guarantee high-quality, testable silicon.

Key Responsibilities

1. Technical Leadership & Solution Architecture

• Act as the technical anchor for DFT methodologies within assigned projects, providing robust solutions and guidance to ensure successful milestones execution.
• Mentor, develop, and guide team members to elevate their technical capabilities, enhancing overall engineering productivity and best practices.
• Participate actively in technical discussions, cross-functional reviews, and ensure strict process compliance within your assigned module.

2. DFT Implementation & Verification Flow

• Ownership of core DFT implementation steps, including Scan insertion, MBIST (Memory Built-In Self-Test) insertion, and BSCAN (Boundary Scan) insertion.
• Execute and drive ATPG (Automatic Test Pattern Generation) Verification to ensure high fault coverage models.
• Utilize and optimize EDA tool flows, specifically focusing on the Mentor Tessent tool suite.

3. Risk Management & Project Reporting

• Proactively identify potential design/test risks, preparing and submitting detailed status reports to minimize project exposure.
• Handle technical escalations effectively and ensure smooth alignment with the digital design and physical design teams for tape-out readiness.

Required Skills & Qualifications

• Education: Bachelor's degree in Electronics Engineering, Electrical Engineering, or an equivalent technical discipline.
• Experience: Minimum 4 years of dedicated experience functioning as a DFT Engineer.
• Core DFT Expertise: Proven hands-on experience in Scan insertion, MBIST insertion, BSCAN insertion, and ATPG Verification.
• Tool Flow: Proficient with industry-standard DFT toolchains, with a strong preference and experience in the Mentor Tessent tool flow.
• Soft Skills:
• • Strong analytical, debugging, and problem-solving mindset.
  • Excellent cross-functional collaboration and leadership communication skills.
  • Good command of English (a strong plus for interfacing with multinational teams).

What We Offer (Benefits & Perks)

• Financial Security: 100% full salary during the probation period, a 13th-month salary, and an attractive Performance Bonus.
• Comprehensive Insurance: An insurance plan calculated based entirely on your full gross salary.
• Premium Healthcare: Medical benefit package covering the employee, with extended family healthcare coverage based on seniority levels.
• Generous Time Off: 18 paid leaves per year (12 annual days + 6 personal days) to maintain a healthy work-life balance.
• Work Schedule: Structured and stable working hours from Monday to Friday.
• Global Exposure: Opportunity to work within a highly diverse, multinational network with the potential for international onsite travel across 49 countries.
• Continuous Growth: Structured internal training pathways covering both Technical & Functional skills, alongside dedicated English language training programs.

About the Client

Our client is a prominent global technology and engineering enterprise with a robust international footprint spanning 49 countries. Recognized for delivering high-performance semiconductor and VLSI solutions, they collaborate with top-tier global teams to design next-generation silicon. They provide a dynamic, fast-paced ecosystem where engineers are empowered to tackle complex chip design challenges and fast-track their technical careers.